Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter

Masum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb. Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016. pages 89-92, IEEE, 2016. [doi]

Abstract

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