A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches

Masashi Tawada, Masao Yanagisawa, Nozomu Togawa. A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Transactions, 96-A(6):1283-1292, 2013. [doi]

Authors

Masashi Tawada

This author has not been identified. Look up 'Masashi Tawada' in Google

Masao Yanagisawa

This author has not been identified. Look up 'Masao Yanagisawa' in Google

Nozomu Togawa

This author has not been identified. Look up 'Nozomu Togawa' in Google