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Masashi Tawada, Masao Yanagisawa, Nozomu Togawa. A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Transactions, 96-A(6):1283-1292, 2013. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded SystemsMasashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa. ipsj, 4:166-181, 2011. [doi]
The following publications are possibly variants of this publication: