Masashi Tawada, Masao Yanagisawa, Nozomu Togawa. A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Transactions, 96-A(6):1283-1292, 2013. [doi]
@article{TawadaYT13, title = {A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches}, author = {Masashi Tawada and Masao Yanagisawa and Nozomu Togawa}, year = {2013}, url = {http://search.ieice.org/bin/summary.php?id=e96-a_6_1283}, researchr = {https://researchr.org/publication/TawadaYT13}, cites = {0}, citedby = {0}, journal = {IEICE Transactions}, volume = {96-A}, number = {6}, pages = {1283-1292}, }