An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding - researchr publication authors

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Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross. An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China. pages 255-260, IEEE, 2007. [doi]

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