Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross. An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China. pages 255-260, IEEE, 2007. [doi]
@inproceedings{TehraniMG07-0,
title = {An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding},
author = {Saeed Sharifi Tehrani and Shie Mannor and Warren J. Gross},
year = {2007},
doi = {10.1109/SIPS.2007.4387554},
url = {http://dx.doi.org/10.1109/SIPS.2007.4387554},
tags = {rule-based, architecture},
researchr = {https://researchr.org/publication/TehraniMG07-0},
cites = {0},
citedby = {0},
pages = {255-260},
booktitle = {Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China},
publisher = {IEEE},
isbn = {1-4244-1222-6},
}