Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications

Erica Tena-Sanchez, Javier Castro-Ramirez, Antonio J. Acosta. Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. In 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014. pages 1-8, IEEE, 2014. [doi]

@inproceedings{Tena-SanchezCA14-1,
  title = {Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications},
  author = {Erica Tena-Sanchez and Javier Castro-Ramirez and Antonio J. Acosta},
  year = {2014},
  doi = {10.1109/PATMOS.2014.6951909},
  url = {http://dx.doi.org/10.1109/PATMOS.2014.6951909},
  researchr = {https://researchr.org/publication/Tena-SanchezCA14-1},
  cites = {0},
  citedby = {0},
  pages = {1-8},
  booktitle = {24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014},
  publisher = {IEEE},
}