Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications

Erica Tena-Sanchez, Javier Castro-Ramirez, Antonio J. Acosta. Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. In 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014. pages 1-8, IEEE, 2014. [doi]

Abstract

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