Table of Contents

• Method to evaluate energy saving techniques in data busesJ. Sanchez, J. M. Gil-Garcia, J. A. Sainz, Miquel Roca, Eugeni Isern. 1-7 [doi]
• A distributed VHDL compiler and simulator accessible from the webMinas Dasygenis. 1-7 [doi]
• Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperatureSebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol. 1-7 [doi]
• A methodology for scaling power dissipation values between different FPGAsAxel Reimer, Wolfgang Nebel. 1-8 [doi]
• Impact of computation offloading on efficiency of wireless face recognitionAkiya Baba, Nanoka Sumi, Vasily G. Moshnyaga. 1-7 [doi]
• A unique network EDA tool to create optimized ad hoc binary to residue number system convertersGiannis Petrousov, Minas Dasygenis. 1-8 [doi]
• A global perspective on energy conservation in large data networksLisa Durbeck, Peter Athanas. 1-9 [doi]
• End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phasesBo Wang 0010, Yang Xu, Ralph Hasholzner, Rafael Rosales, Michael Glaß, Jürgen Teich. 1-8 [doi]
• Energy management of highly dynamic server workloads in an heterogeneous data centerEfraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yassin, Ran Ginosar. 1-5 [doi]
• Gate leakage current accurate models for nanoscale MOSFET transistorsAbdoul Rjoub, Nedal Al Taradeh, Mamoun F. Al-Mistarihi. 1-4 [doi]
• A power-efficient FPGA-based self-adaptive software defined radioChris Dobson, Kurt Rooks, Peter M. Athanas. 1-8 [doi]
• An analytical model for the CMOS inverterPanagiotis Chaourani, I. Messaris, N. Fasarakis, M. Ntogramatzi, S. Goudos, Spiros Nikolaidis. 1-6 [doi]
• Hardware-assisted power estimation for design-stage processors using FPGA emulationSebastian Hesselbarth, Tim Baumgart, Holger Blume. 1-8 [doi]
• Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devicesAlexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis. 1-8 [doi]
• Robust sub-powered asynchronous logicJiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana. 1-7 [doi]
• Fast energy evaluation of embedded applications for many-core systemsFelipe Rosa, Luciano Ost, Thiago Raupp, Fernando Gehm Moraes, Ricardo Reis. 1-6 [doi]
• Energy consumption savings in ZigBee-based WSN adjusting power transmission at application layerC. Carmona, Bartomeu Alorda, Miquel A. Ribot. 1-6 [doi]
• GALS design of ECC against side-channel attacks - A comparative studyXin Fan, Steffen Peter, Milos Krstic. 1-6 [doi]
• Write scheme for multiple Complementary Resistive Switch (CRS) cellsAdedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan. 1-5 [doi]
• Convex optimization of resource allocation in asymmetric and heterogeneous SoCAmir Morad, Leonid Yavits, Ran Ginosar. 1-8 [doi]
• Low-cost hardware implementation of Reservoir ComputersM. L. Alomar, Vicent Canals, V. Martinez-Moll, Josep L. Rosselló. 1-5 [doi]
• Parametric yield optimization using leakage-yield-driven floorplanningYang Xu, Bo Wang 0010, Jürgen Teich. 1-6 [doi]
• Advanced SoC virtual prototyping for system-level power planning and validationFabian Mischkalla, Wolfgang Mueller. 1-8 [doi]
• Application-aware scaling governor for wearable devicesJae Min Kim, Minyong Kim, Sung Woo Chung. 1-8 [doi]
• Power efficient digital IC design for a medical application with high reliability requirementsNasim Pour Aryan, Nils Heidmann, Martin Wirnshofer, Nico Hellwege, Jonas Pistor, Dagmar Peters-Drolshagen, Georg Georgakos, Steffen Paul, Doris Schmitt-Landsiedel. 1-5 [doi]
• A scalable physical model for Nano-Electro-Mechanical relaysHaider Alrudainy, Andrey Mokhov, Alex Yakovlev. 1-7 [doi]
• Optimization on cell-library design for digital Application Specific Printed Electronics CircuitsManuel Llamas, Mohammad Mashayekhi, Jordi Carrabina, Jody Maick Matos, André Inácio Reis. 1-6 [doi]
• Rate-distortion and energy performance of HEVC video encodersEduarda Monteiro, Mateus Grellert, Bruno Zatt, Sergio Bampi. 1-8 [doi]
• Fast modeling technique for nano scale CMOS inverter and propagation delay estimationAbdoul Rjoub, Areej Ahmad. 1-4 [doi]
• Fast and accurate solution for power estimation and DPA countermeasure designDaniel Vidal, Mario L. Côrtes. 1-7 [doi]
• Formal description of an approach for power consumption estimation of embedded systemsDmitriy Shorin, Armin Zimmermann. 1-10 [doi]
• A lightweight-system-level power and area estimation methodology for application specific instruction set processorsSyed Abbas Ali Shah, Jan Wagner, Thomas Schuster, Mladen Berekovic. 1-5 [doi]
• VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platformsSanthosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal. 1-8 [doi]
• Tuning software-based fault-tolerance techniques for power optimizationEduardo Chielle, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi. 1-7 [doi]
• Estimating power consumption of multiple modular redundant designs in SRAM-based FPGAs for high dependable applicationsJimmy Tarrillo, Fernanda Lima Kastensmidt. 1-7 [doi]
• Low-power design methodology for CML and ECL circuitsOliver Schrape, Markus Appel, Frank Winkler, Milos Krstic. 1-5 [doi]
• DOE based high-performance gate-level pipelinesJuan Núñez, Maria J. Avedillo, Hector J. Quintero. 1-4 [doi]
• Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applicationsErica Tena-Sanchez, Javier Castro-Ramirez, Antonio J. Acosta. 1-8 [doi]
• Power-efficient power-management logicDominik Macko, Katarina Jelemenska, Pavel Cicak. 1-7 [doi]
• A framework for efficient evaluation and comparison of EES ModelsSara Vinco, Alessandro Sassone, Davide Lasorsa, Enrico Macii, Massimo Poncino. 1-8 [doi]
• Efficient Dense and Sparse Matrix Multiplication on GP-SIMDAmir Morad, Leonid Yavits, Ran Ginosar. 1-8 [doi]
• Power-efficient turbo-decoder design based on algorithm-specific power domain partitioningChristoph Roth, Christian Benkeser, Qiuting Huang. 1-6 [doi]
• Equivalence of clock gating and synchronization with applicability to GALS communicationRobert Najvirt, Andreas Steininger. 1-8 [doi]