Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto. Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. In IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009. pages 104-105, IEEE, 2009. [doi]

This author has not been identified. Look up 'Jun Terada' in GoogleThis author has not been identified. Look up 'Yusuke Ohtomo' in GoogleThis author has not been identified. Look up 'Kazuyoshi Nishimura' in GoogleThis author has not been identified. Look up 'Hiroaki Katsurai' in GoogleThis author has not been identified. Look up 'Shunji Kimura' in GoogleThis author has not been identified. Look up 'Naoto Yoshimoto' in Google

runs on WebDSL