Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano. Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. In Dirk Koch, Satnam Singh, Jim Tørresen, editors, 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012. pages 639-642, IEEE, 2012. [doi]
@inproceedings{TeradaUISTU12,
title = {Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs},
author = {Kazuhiko Terada and Hiroyuki Uzawa and Namiko Ikeda and Satoshi Shigematsu and Nobuyuki Tanaka and Masami Urano},
year = {2012},
doi = {10.1109/FPL.2012.6339229},
url = {http://dx.doi.org/10.1109/FPL.2012.6339229},
researchr = {https://researchr.org/publication/TeradaUISTU12},
cites = {0},
citedby = {0},
pages = {639-642},
booktitle = {22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012},
editor = {Dirk Koch and Satnam Singh and Jim Tørresen},
publisher = {IEEE},
isbn = {978-1-4673-2257-7},
}