Balancing Logic Utilization and Area Efficiency in FPGAs

Russell Tessier, Heather Giza. Balancing Logic Utilization and Area Efficiency in FPGAs. In Reiner W. Hartenstein, Herbert Grünbacher, editors, Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings. Volume 1896 of Lecture Notes in Computer Science, pages 535-544, Springer, 2000. [doi]

@inproceedings{TessierG00,
  title = {Balancing Logic Utilization and Area Efficiency in FPGAs},
  author = {Russell Tessier and Heather Giza},
  year = {2000},
  url = {http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=1896&spage=0535},
  tags = {logic},
  researchr = {https://researchr.org/publication/TessierG00},
  cites = {0},
  citedby = {0},
  pages = {535-544},
  booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings},
  editor = {Reiner W. Hartenstein and Herbert Grünbacher},
  volume = {1896},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer},
  isbn = {3-540-67899-9},
}