A parallel preconditioning strategy for efficient transistor-level circuit simulation

Heidi Thornquist, Eric R. Keiter, Robert J. Hoekstra, David M. Day, Erik G. Boman. A parallel preconditioning strategy for efficient transistor-level circuit simulation. In 2009 International Conference on Computer-Aided Design (ICCAD 09), November 2-5, 2009, San Jose, CA, USA. pages 410-417, IEEE, 2009. [doi]

Authors

Heidi Thornquist

This author has not been identified. Look up 'Heidi Thornquist' in Google

Eric R. Keiter

This author has not been identified. Look up 'Eric R. Keiter' in Google

Robert J. Hoekstra

This author has not been identified. Look up 'Robert J. Hoekstra' in Google

David M. Day

This author has not been identified. Look up 'David M. Day' in Google

Erik G. Boman

This author has not been identified. Look up 'Erik G. Boman' in Google