A parallel preconditioning strategy for efficient transistor-level circuit simulation

Heidi Thornquist, Eric R. Keiter, Robert J. Hoekstra, David M. Day, Erik G. Boman. A parallel preconditioning strategy for efficient transistor-level circuit simulation. In 2009 International Conference on Computer-Aided Design (ICCAD 09), November 2-5, 2009, San Jose, CA, USA. pages 410-417, IEEE, 2009. [doi]

@inproceedings{ThornquistKHDB09,
  title = {A parallel preconditioning strategy for efficient transistor-level circuit simulation},
  author = {Heidi Thornquist and Eric R. Keiter and Robert J. Hoekstra and David M. Day and Erik G. Boman},
  year = {2009},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5361259},
  researchr = {https://researchr.org/publication/ThornquistKHDB09},
  cites = {0},
  citedby = {0},
  pages = {410-417},
  booktitle = {2009 International Conference on Computer-Aided Design (ICCAD 09), November 2-5, 2009, San Jose, CA, USA},
  publisher = {IEEE},
}