Delay-Time Modeling for ED MOS Logic LSI

Takeshi Tokuda, Kaoru Okazaki, K. Sakashita, I. Ohkura, T. Enomoto. Delay-Time Modeling for ED MOS Logic LSI. IEEE Trans. on CAD of Integrated Circuits and Systems, 2(3):129-134, 1983. [doi]

Authors

Takeshi Tokuda

This author has not been identified. Look up 'Takeshi Tokuda' in Google

Kaoru Okazaki

This author has not been identified. Look up 'Kaoru Okazaki' in Google

K. Sakashita

This author has not been identified. Look up 'K. Sakashita' in Google

I. Ohkura

This author has not been identified. Look up 'I. Ohkura' in Google

T. Enomoto

This author has not been identified. Look up 'T. Enomoto' in Google