Delay-Time Modeling for ED MOS Logic LSI

Takeshi Tokuda, Kaoru Okazaki, K. Sakashita, I. Ohkura, T. Enomoto. Delay-Time Modeling for ED MOS Logic LSI. IEEE Trans. on CAD of Integrated Circuits and Systems, 2(3):129-134, 1983. [doi]

Abstract

Abstract is missing.