Nobuhiro Tomabechi. Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems. In Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989. pages 362-365, IEEE, 1989. [doi]
@inproceedings{Tomabechi89,
title = {Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems},
author = {Nobuhiro Tomabechi},
year = {1989},
doi = {10.1109/ICCD.1989.63388},
url = {https://doi.org/10.1109/ICCD.1989.63388},
researchr = {https://researchr.org/publication/Tomabechi89},
cites = {0},
citedby = {0},
pages = {362-365},
booktitle = {Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989},
publisher = {IEEE},
isbn = {0-8186-1971-6},
}