Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers

Nobuhiro Tomabechi, Teruki Ito. Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers. In IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings. pages 697-700, IEEE, 2000. [doi]

Abstract

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