Nobuhiro Tomabechi, Teruki Ito. Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers. In Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001. pages 267-271, IEEE, 2001. [doi]
@inproceedings{TomabechiI01,
title = {Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers},
author = {Nobuhiro Tomabechi and Teruki Ito},
year = {2001},
doi = {10.1109/ICECS.2001.957731},
url = {https://doi.org/10.1109/ICECS.2001.957731},
researchr = {https://researchr.org/publication/TomabechiI01},
cites = {0},
citedby = {0},
pages = {267-271},
booktitle = {Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001},
publisher = {IEEE},
isbn = {0-7803-7057-0},
}