Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers - researchr publication

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Nobuhiro Tomabechi, Teruki Ito. Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers. In Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001. pages 267-271, IEEE, 2001. [doi]

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