A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications - researchr publication related

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Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada. A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications. IEICE Transactions, 90-C(10):1957-1963, 2007. [doi]

The following publications are possibly variants of this publication:

A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane EthernetHidehiro Toyoda, Michitaka Okuno, Shinji Nishimura, Matsuaki Terada. icc 2008: 5417-5421 [doi]

100-Gb/s Physical-Layer Architecture for Next-Generation EthernetHidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi. ieicet, 89-B(3):696-703, 2006. [doi]

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