Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix-vector multiplication

James D. Trotter, Johannes Langguth, Xing Cai. Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix-vector multiplication. J. Parallel Distrib. Comput., 144:189-205, 2020. [doi]

Authors

James D. Trotter

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Johannes Langguth

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Xing Cai

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