A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth - researchr publication authors

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Chih Tseng, Jae-Hyeong Kim, S. Chen, Mu-Hsiang Huang, Chungji Lu, I. Hashiguchi, Y. Miyazima, M. Ichihashi, K. Maki, K. Nakashima, P. Chuang. A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 2582-2591, IEEE, 2006. [doi]

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