Chih Tseng, Jae-Hyeong Kim, S. Chen, Mu-Hsiang Huang, Chungji Lu, I. Hashiguchi, Y. Miyazima, M. Ichihashi, K. Maki, K. Nakashima, P. Chuang. A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 2582-2591, IEEE, 2006. [doi]
@inproceedings{TsengKCHLHMIMNC06,
title = {A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth},
author = {Chih Tseng and Jae-Hyeong Kim and S. Chen and Mu-Hsiang Huang and Chungji Lu and I. Hashiguchi and Y. Miyazima and M. Ichihashi and K. Maki and K. Nakashima and P. Chuang},
year = {2006},
doi = {10.1109/ISSCC.2006.1696324},
url = {https://doi.org/10.1109/ISSCC.2006.1696324},
researchr = {https://researchr.org/publication/TsengKCHLHMIMNC06},
cites = {0},
citedby = {0},
pages = {2582-2591},
booktitle = {2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006},
publisher = {IEEE},
isbn = {1-4244-0079-1},
}