On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs

Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose. On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. In International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan. pages 1565-1568, IEEE, 2009. [doi]

Authors

Yusuke Tsugita

This author has not been identified. Look up 'Yusuke Tsugita' in Google

Ken Ueno

This author has not been identified. Look up 'Ken Ueno' in Google

Tetsuya Asai

This author has not been identified. Look up 'Tetsuya Asai' in Google

Yoshihito Amemiya

This author has not been identified. Look up 'Yoshihito Amemiya' in Google

Tetsuya Hirose

This author has not been identified. Look up 'Tetsuya Hirose' in Google