On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs

Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose. On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. In International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan. pages 1565-1568, IEEE, 2009. [doi]

Abstract

Abstract is missing.