R. Udaiyakumar, Senoj Joseph, T. V. P. Sundararajan, D. Vigneswaran, R. Maheswar, Iraj S. Amiri. Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture. Wireless Personal Communications, 102(4):3477-3488, 2018. [doi]
@article{UdaiyakumarJSVM18,
title = {Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture},
author = {R. Udaiyakumar and Senoj Joseph and T. V. P. Sundararajan and D. Vigneswaran and R. Maheswar and Iraj S. Amiri},
year = {2018},
doi = {10.1007/s11277-018-5385-2},
url = {https://doi.org/10.1007/s11277-018-5385-2},
researchr = {https://researchr.org/publication/UdaiyakumarJSVM18},
cites = {0},
citedby = {0},
journal = {Wireless Personal Communications},
volume = {102},
number = {4},
pages = {3477-3488},
}