Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture - researchr publication

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R. Udaiyakumar, Senoj Joseph, T. V. P. Sundararajan, D. Vigneswaran, R. Maheswar, Iraj S. Amiri. Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture. Wireless Personal Communications, 102(4):3477-3488, 2018. [doi]

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