A Timing Model for VLSI CMOS Circuits Verification and Optimization - researchr publication bibtex

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Luís Felipe Uebel, Sergio Bampi. A Timing Model for VLSI CMOS Circuits Verification and Optimization. In ISCAS. pages 439-442, 1994.

@inproceedings{UebelB94,
  title = {A Timing Model for VLSI CMOS Circuits Verification and Optimization},
  author = {Luís Felipe Uebel and Sergio Bampi},
  year = {1994},
  tags = {optimization},
  researchr = {https://researchr.org/publication/UebelB94},
  cites = {0},
  citedby = {0},
  pages = {439-442},
  booktitle = {ISCAS},
}

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