High Throughput/Gate AES Hardware Architectures Based on Datapath Compression - researchr publication authors

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Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger. High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Transactions on Computers, 69(4):534-548, 2020. [doi]

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