The following publications are possibly variants of this publication:
- A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode ImplementationRei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki. iacr, 2016:595, 2016. [doi]
- A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode ImplementationRei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki. ches 2016: 538-558 [doi]
- High Throughput/Gate FN-Based Hardware Architectures for AES-OTRRei Ueno, Naofumi Homma, Tomonori Iida, Kazuhiko Minematsu. iscas 2019: 1-4 [doi]