Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura. QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 216-218, IEEE, 2018. [doi]
@inproceedings{UeyoshiAHTKMHKM18,
title = {QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS},
author = {Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Junichiro Kadomoto and Tomoki Miyata and Mototsugu Hamada and Tadahiro Kuroda and Masato Motomura},
year = {2018},
doi = {10.1109/ISSCC.2018.8310261},
url = {https://doi.org/10.1109/ISSCC.2018.8310261},
researchr = {https://researchr.org/publication/UeyoshiAHTKMHKM18},
cites = {0},
citedby = {0},
pages = {216-218},
booktitle = {2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018},
publisher = {IEEE},
isbn = {978-1-5090-4940-0},
}