Stephen H. Unger. Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors. IEEE Design & Test of Computers, 20(6):18-24, 2003. [doi]
@article{Unger03,
title = {Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors},
author = {Stephen H. Unger},
year = {2003},
url = {http://csdl.computer.org/comp/mags/dt/2003/06/d6018abs.htm},
tags = {logic},
researchr = {https://researchr.org/publication/Unger03},
cites = {0},
citedby = {0},
journal = {IEEE Design & Test of Computers},
volume = {20},
number = {6},
pages = {18-24},
}