An hybrid eDRAM/SRAM macrocell to implement first-level data caches - researchr publication authors

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Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro LÃ³pez, JosÃ© Duato. An hybrid eDRAM/SRAM macrocell to implement first-level data caches. In David H. Albonesi, Margaret Martonosi, David I. August, JosÃ© MartÃnez, editors, 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA. pages 213-221, ACM, 2009. [doi]

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Julio Sahuquillo

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