Table of Contents

• POWER7 multi-core processor designBalaram Sinharoy. 1 [doi]
• Characterizing and mitigating the impact of process variations on phase change based memory systemsWangyuan Zhang, Tao Li. 2-13 [doi]
• Enhancing lifetime and security of PCM-based main memory with start-gap wear levelingMoinuddin K. Qureshi, John Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis Lastras, Bülent Abali. 14-23 [doi]
• Characterizing flash memory: anomalies, observations, and applicationsLaura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, Jack K. Wolf. 24-33 [doi]
• Complexity effective memory access scheduling for many-core accelerator architecturesGeorge L. Yuan, Ali Bakhoda, Tor M. Aamodt. 34-44 [doi]
• Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mappingChi-Keung Luk, Sunpyo Hong, Hyesoon Kim. 45-55 [doi]
• DDT: design and evaluation of a dynamic program analysis for optimizing data structure usageChanghee Jung, Nathan Clark. 56-66 [doi]
• Tree register allocationHongbo Rong. 67-77 [doi]
• Portable compiler optimisation across embedded programs and microarchitectures using machine learningChristophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O Boyle. 78-88 [doi]
• Improving cache lifetime reliability at ultra-low voltagesZeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu. 89-99 [doi]
• ZerehCache: armoring cache architectures in high defect density technologiesAmin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke. 100-110 [doi]
• Low Vccmin fault-tolerant cache with highly predictable performanceJaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González. 111-121 [doi]
• mSWAT: low-cost hardware fault detection and diagnosis for multicore systemsSiva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve. 122-132 [doi]
• BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware supportWonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, J. W. Lee, Xing Fang, Samuel P. Midkiff, David Wong. 133-144 [doi]
• EazyHTM: eager-lazy hardware transactional memorySasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero. 145-155 [doi]
• Proactive transaction scheduling for contention managementGeoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge. 156-167 [doi]
• Into the wild: studying real user activity patterns to guide power optimizations for mobile architecturesAlex Shye, Benjamin Scholbrock, Gokhan Memik. 168-178 [doi]
• A microarchitecture-based framework for pre- and post-silicon power delivery analysisMahesh Ketkar, Eli Chiprout. 179-188 [doi]
• Reducing peak power with a table-driven adaptive processor coreVasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar. 189-200 [doi]
• Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policyGabriel H. Loh. 201-212 [doi]
• An hybrid eDRAM/SRAM macrocell to implement first-level data cachesAlejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato. 213-221 [doi]
• Variation-tolerant non-uniform 3D cache management in die stacked multicore processorBo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002. 222-231 [doi]
• In-network coherence filtering: snoopy coherence without broadcastsNiket Agarwal, Li-Shiuan Peh, Niraj K. Jha. 232-243 [doi]
• SCARAB: a single cycle adaptive routing and bufferless networkMitchell Hayenga, Natalie D. Enright Jerger, Mikko H. Lipasti. 244-254 [doi]
• Low-cost router microarchitecture for on-chip networksJohn Kim. 255-266 [doi]
• Why design must change: rethinking digital designMark Horowitz. 267 [doi]
• Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chipBoris Grot, Stephen W. Keckler, Onur Mutlu. 268-279 [doi]
• Application-aware prioritization mechanisms for on-chip networksReetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das. 280-291 [doi]
• A case for dynamic frequency tuning in on-chip networksAsit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar Iyer, Narayanan Vijaykrishnan, Chita R. Das. 292-303 [doi]
• Light speed arbitration and flow control for nanophotonic interconnectsDana Vantrease, Nathan L. Binkert, Robert Schreiber, Mikko H. Lipasti. 304-315 [doi]
• Coordinated control of multiple prefetchers in multi-core systemsEiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt. 316-326 [doi]
• Improving memory bank-level parallelism in the presence of prefetchingChang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt. 327-336 [doi]
• ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystemCiji Isen, Lizy Kurian John. 337-346 [doi]
• Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and enduranceSangyeun Cho, Hyunjin Lee. 347-357 [doi]
• Using a configurable processor generator for computer architecture prototypingAlex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz. 358-369 [doi]
• Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applicationsHyunchul Park, Yongjun Park, Scott A. Mahlke. 370-380 [doi]
• Ordering decoupled metadata accesses in multiprocessorsHari Kannan. 381-390 [doi]
• Control flow obfuscation with information flow trackingHaibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huang, Pen-Chung Yew. 391-400 [doi]
• Pseudo-LIFO: the foundation of a new family of replacement policies for last-level cachesMainak Chaudhuri. 401-412 [doi]
• Comparing cache architectures and coherency protocols on x86-64 multicore SMP systemsDaniel Hackenberg, Daniel Molka, Wolfgang E. Nagel. 413-422 [doi]
• A tagless coherence directoryJason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos. 423-434 [doi]
• Tribeca: design for PVT variations with local recovery and fine-grained adaptationMeeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks. 435-446 [doi]
• The BubbleWrap many-core: popping cores for sequential accelerationUlya R. Karpuzcu, Brian Greskamp, Josep Torrellas. 447-458 [doi]
• Multiple clock and voltage domains for chip multi processorsEfraim Rotem, Avi Mendelson, Ran Ginosar, Uri Weiser. 459-468 [doi]
• McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architecturesSheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi. 469-480 [doi]
• Characterizing the resource-sharing levels in the UltraSPARC T2 processorVladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero. 481-492 [doi]
• Execution leases: a hardware-supported mechanism for enforcing strong non-interferenceMohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederic T. Chong, Timothy Sherwood. 493-504 [doi]
• Optimizing shared cache behavior of chip multiprocessorsMahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk. 505-516 [doi]
• SHARP control: controlled shared cache management in chip multiprocessorsShekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang. 517-528 [doi]
• Adaptive line placement with the ::::set balancing cache::::Dyer Rolán, Basilio B. Fraguela, Ramon Doallo. 529-540 [doi]
• Light64: lightweight hardware support for data race detection during systematic testing of parallel programsAdrian Nistor, Darko Marinov, Josep Torrellas. 541-552 [doi]
• Finding concurrency bugs with context-aware communication graphsBrandon Lucia, Luis Ceze. 553-563 [doi]
• Offline symbolic analysis for multi-processor execution replayDongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang, Cristiano Pereira. 564-575 [doi]
• Architecting a chunk-based memory race recorder in modern CMPsGilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai. 576-585 [doi]