A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU

Lan-Da Van, Tao-Jung Wang, Sing-Jia Tzeng, Tzyy-Ping Jung. A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU. In 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23, 2021. pages 171-177, IEEE, 2021. [doi]

Abstract

Abstract is missing.