Table of Contents

• FPGA-Based Implementation of the Stereo Matching Algorithm Using High-Level SynthesisIman Firmansyah, Yoshiki Yamaguchi. 1-7 [doi]
• Acceleration of Gravitation Field Analysis for Asteroids by GPU ComputationFumiya Kono, Naohito Nakasato, Naru Hirata, Koji Matsumoto. 8-15 [doi]
• Accelerated on-Chip Algorithm Based on Semantic Region-Based Partial Difference Detection for LiDAR-Vision Depth Data Transmission Reduction in Lightweight Controller Systems of Autonomous VehicleDongkyu Jung, Daejin Park. 16-22 [doi]
• Host Bypassing: Direct Data Piping from the Network to the Hardware AcceleratorRalf Kundel, Kadir Eryigit, Jonas Markussen, Carsten Griwodz, Osama Abboud, Rhaban Hark, Ralf Steinmetz. 23-30 [doi]
• A function-rich FPGA system of camera image processing for video meetingTakashi Odan, Takuto Kanamori, Kenji Kise. 31-37 [doi]
• RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructionsTakuto Kanamori, Kenji Kise. 38-45 [doi]
• Execution Right Delegation Scheduling Algorithm for MultiprocessorTakaharu Suzuki, Kiyofumi Tanaka. 46-53 [doi]
• Scheduling DAGs of Multi-Version Multi-Phase Tasks on Heterogeneous Real-Time SystemsJulius Roeder, Benjamin Rouxel, Clemens Grelck. 54-61 [doi]
• SIMD Parallel Execution on GPU from High-Level Dataflow SynthesisAurelien Bloch, Simone Casale Brunet, Marco Mattavelli. 62-68 [doi]
• Performance Estimation of High-Level Dataflow Program on Heterogeneous PlatformsAurelien Bloch, Simone Casale Brunet, Marco Mattavelli. 69-76 [doi]
• Parallel Implementation of CNN on Multi-FPGA ClusterYasuyu Fukushima, Kensuke Iizuka, Hideharu Amano. 77-83 [doi]
• A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGAFumio Hamanaka, Takuto Kanamori, Kenji Kise. 84-91 [doi]
• A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write ShiftingDaisuke Suzuki, Takahiro Oka, Takahiro Hanyu. 92-97 [doi]
• Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor NodesShaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura. 98-105 [doi]
• MSCU: Accelerating CNN Inference with Multiple Sizes of Compute Unit on FPGAsZhenshan Bao, Junnan Guo, Xiaqing Li, Wenbo Zhang 0003. 106-113 [doi]
• Variable Bit-Precision Vector Extension for RISC-V Based ProcessorsRisikesh RK, Sharad Sinha, Nanditha Rao. 114-121 [doi]
• Parasitic-Aware Modelling for Neural Networks Implemented with Memristor Crossbar ArrayTiancheng Cao, Chen Liu, Yuan Gao, Wang Ling Goh. 122-126 [doi]
• Distributed Neural Network with TensorFlow on Human Activity Recognition Over Multicore TPUHaklin Kimm, Incheon Paik. 127-134 [doi]
• EEG-based Positive-Negative Emotion Classification Using Machine Learning TechniquesYuta Kasuga, Jungpil Shin, Md. Al Mehedi Hasan, Yuichi Okuyama, Yoichi Tomioka. 135-139 [doi]
• CNN-based End-to-end Autonomous Driving on FPGA Using TVM and VTAToshihiro Uetsuki, Yuichi Okuyama, Jungpil Shin. 140-144 [doi]
• Surface Type Classification for Autonomous Robots Using Temporal, Statistical and Spectral Feature Extraction and SelectionMd. Al Mehedi Hasan, Fuad Al Abir, Jungpil Shin. 145-150 [doi]
• A Multi-scale Binarized Neural Network Application Based on All Programmable System on ChipMaoyang Xiang, T. Hui Teo. 151-156 [doi]
• Data Fusion Driven Lane-level Precision Data Transmission for V2X Road ApplicationsAlbert Budi Christian, Chih-Yu Lin, Lan-Da Van, Yu-Chee Tseng. 157-163 [doi]
• A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific OptimizationsZikang Zhou, Chao Fu, Ruiqi Xie, Jun Han. 164-170 [doi]
• A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPULan-Da Van, Tao-Jung Wang, Sing-Jia Tzeng, Tzyy-Ping Jung. 171-177 [doi]
• A Distance Estimation Method to Railway Crossing Using Warning SignsKaisei Shimura, Yoichi Tomioka, Qiangfu Zhao. 178-181 [doi]
• Dynamic Service Recommendation Using Lightweight BERT-based Service Embedding in Edge ComputingKungan Zeng, Incheon Paik. 182-189 [doi]
• Light-weight Enhanced Semantics-Guided Neural Networks for Skeleton-Based Human Action RecognitionHongbo Chen, Lei Jing. 190-196 [doi]
• Ising-Based Combinatorial Clustering Using the Kernel MethodMasahito Kumagai, Kazuhiko Komatsu, Masayuki Sato 0001, Hiroaki Kobayashi. 197-203 [doi]
• FPGA based Adaptive Hardware Acceleration for Multiple Deep Learning TasksYufan Lu, Xiaojun Zhai, Sangeet Saha, Shoaib Ehsan, Klaus D. McDonald-Maier. 204-209 [doi]
• Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance CountersPavitra Prakash Bhade, Sharad Sinha. 210-217 [doi]
• 2QoSM: A Q-Learner QoS Manager for Application-Guided Power-Aware SystemsMichael J. Giardino, Daniel Schwyn, Bonnie H. Ferri, Aldo A. Ferri. 218-225 [doi]
• Trends and Challenges in Ensuring Security for Low-Power and High-Performance Embedded SoCsParisa Rahimi, Amit Kumar Singh 0002, Xiaohang Wang, Alok Prakash. 226-233 [doi]
• Task Scheduling Strategies for Batched Basic Linear Algebra Subprograms on Many-core CPUsDaichi Mukunoki, Yusuke Hirota, Toshiyuki Imamura. 234-241 [doi]
• Portability of Vectorization-aware Performance Tuning Expertise across System GenerationsShunpei Sugawara, Yoichi Shimomura, Ryusuke Egawa, Hiroyuki Takizawa. 242-248 [doi]
• Enhancing Autotuning Capability with a History DatabaseYounghyun Cho, James Demmel, Xiaoye S. Li, Yang Liu, Hengrui Luo. 249-257 [doi]
• Sparse Matrix Ordering Method with a Quantum Annealing Approach and its Parameter TuningTomoko Komiyama, Tomohiro Suzuki. 258-264 [doi]
• A Highly Efficient Layout-Aware FPGA Overlay Accelerator Mapping MethodTanvir Ahmed, Johannes Maximilian Kühn, Ken Namura. 265-272 [doi]
• Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flopsAika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho. 273-280 [doi]
• Multiport Register File Design for High-Performance Embedded CoresJunichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 281-286 [doi]
• Text Compression Based on an Alternative Approach of Run-Length Coding Using Burrows-Wheeler Transform and Arithmetic CodingMd. Atiqur Rahman, Mohamed Hamada 0001, Md. Asfaqur Rahman. 287-291 [doi]
• UI Method to Support Knowledge Creation in Hybrid Museum ExperienceToru Tamahashi, Rentaro Yoshioka, Takayuki Hoshino. 292-295 [doi]
• Design of a Knowledge Experience Based Environment for Museum Data Exploration and Knowledge CreationTakayuki Hoshino, Rentaro Yoshioka, Yukihide Kohira. 296-303 [doi]
• Mini-Batch Training along Convolution Windows for Representation Learning Based on Spike-Time-Dependent-Plasticity RuleYohei Shimmyo, Yuichi Okuyama. 304-311 [doi]
• Performance Comparision of TPU, GPU, CPU on Google Colaboratory Over Distributed Deep LearningHaklin Kimm, Incheon Paik, Hanke Kimm. 312-319 [doi]
• A Network Simulator for the Estimation of Bandwidth Load and Latency Created by Heterogeneous Spiking Neural Networks on Neuromorphic Computing Communication NetworksR. Kleijnen, Markus Robens, Michael Schiek, Stefan van Waasen. 320-327 [doi]
• Configuring an Embedded Neuromorphic Coprocessor Using a RISC-V Chip for Enabling Edge Computing ApplicationsEvelina Forno, Andrea Spitale, Enrico Macii, Gianvito Urgese. 328-332 [doi]
• Evaluation of Recursive Feature Elimination and LASSO Regularization-based optimized feature selection approaches for cervical cancer predictionMohamed Hamada 0001, Jesse Jeremiah Tanimu, Mohammed Hassan, Habeebah Adamu Kakudi, Patience Robert. 333-339 [doi]
• The Role of Linear Discriminant Analysis for Accurate Prediction of Breast CancerEgwom Onyinyechi Jessica, Mohamed Hamada 0001, Saratu Ilu Yusuf, Mohammed Hassan. 340-344 [doi]
• An Intelligent Plant Dissease Detection System for Smart Hydroponic Using Convolutional Neural NetworkAminu Musa, Mohamed Hamada 0001, Farouq Muhammad Aliyu, Mohammed Hassan. 345-351 [doi]
• A Framework and Its User Interface to Learn Machine Learning ModelsAtsushi Takamiya, Md. Mostafizer Rahman, Yutaka Watanobe. 352-358 [doi]
• Boosting CPU Performance using Pipelined Branch and Jump Folding Hardware with Turbo ModuleMong Tee Sim. 359-365 [doi]
• Efficient Resource Shared RISC-V Multicore ProcessorMd. Ashraful Islam, Kenji Kise. 366-372 [doi]
• Task-level Redundancy vs Instruction-level Redundancy against Single Event Upsets in Real-time DAG schedulingLukas Miedema, Benjamin Rouxel, Clemens Grelck. 373-380 [doi]
• RELAX: a REconfigurabLe Approximate Network-on-ChipRichard Fenster, Sébastien Le Beux. 381-387 [doi]
• Analyzable Publish-Subcribe Communication Through a Wait-Free FIFO Channel for MPSoC Real-Time ApplicationsSaeid Dehnavi, Dip Goswami, Kees Goossens. 388-395 [doi]
• LUSH: Lightweight Framework for User-level Scheduling in Heterogeneous MulticoresVasco Miguel Liang Xu, Liam White McShane, Daniel Mossé. 396-404 [doi]
• An Architecture to Enable Machine-Learning-Based Task Migration for Multi-Core Real-Time SystemsOctavio Delgadillo, Bernhard Blieninger, Juri Kuhn, Uwe Baumgarten. 405-412 [doi]