Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs

Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, Sai Pentapati, Yun Heo, Jae-Seung Choi, Sung Kyu Lim. Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems, 42(7):2331-2335, July 2023. [doi]

@article{VannaIampikulSLPHCL23,
  title = {Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs},
  author = {Pruek Vanna-Iampikul and Chengjia Shao and Yi-Chen Lu and Sai Pentapati and Yun Heo and Jae-Seung Choi and Sung Kyu Lim},
  year = {2023},
  month = {July},
  doi = {10.1109/TCAD.2022.3218763},
  url = {https://doi.org/10.1109/TCAD.2022.3218763},
  researchr = {https://researchr.org/publication/VannaIampikulSLPHCL23},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {42},
  number = {7},
  pages = {2331-2335},
}