Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs

Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, Sai Pentapati, Yun Heo, Jae-Seung Choi, Sung Kyu Lim. Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems, 42(7):2331-2335, July 2023. [doi]

Abstract

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