A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems

Eduardo de Vasconcelos, Rui L. Aguiar, Dinis M. Santos. A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems. In 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998 . pages 411-414, IEEE, 1998. [doi]

@inproceedings{VasconcelosAS98,
  title = {A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems},
  author = {Eduardo de Vasconcelos and Rui L. Aguiar and Dinis M. Santos},
  year = {1998},
  doi = {10.1109/ICECS.1998.814019},
  url = {https://doi.org/10.1109/ICECS.1998.814019},
  researchr = {https://researchr.org/publication/VasconcelosAS98},
  cites = {0},
  citedby = {0},
  pages = {411-414},
  booktitle = {5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998 },
  publisher = {IEEE},
  isbn = {0-7803-5008-1},
}