Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

Zdenek Vasícek, Lukás Sekanina. Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genetic Programming and Evolvable Machines, 12(3):305-327, 2011. [doi]

Authors

Zdenek Vasícek

This author has not been identified. Look up 'Zdenek Vasícek' in Google

Lukás Sekanina

This author has not been identified. Look up 'Lukás Sekanina' in Google