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Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations

M. Vazquez, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps. Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. In Viktor K. Prasanna, Lionel Torres, René Cumplido, editors, ReConFig 09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings. pages 42-47, IEEE Computer Society, 2009. [doi]

Authors

M. Vazquez

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Gustavo Sutter

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Gery Bioul

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Jean-Pierre Deschamps

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