Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs - researchr publication authors

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Rajesh Velegalati, Jens-Peter Kaps. Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs. In International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece. pages 506-511, IEEE, 2011. [doi]

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