Rajesh Velegalati, Jens-Peter Kaps. Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs. In International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece. pages 506-511, IEEE, 2011. [doi]
@inproceedings{VelegalatiK11,
title = {Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs},
author = {Rajesh Velegalati and Jens-Peter Kaps},
year = {2011},
doi = {10.1109/FPL.2011.100},
url = {http://doi.ieeecomputersociety.org/10.1109/FPL.2011.100},
researchr = {https://researchr.org/publication/VelegalatiK11},
cites = {0},
citedby = {0},
pages = {506-511},
booktitle = {International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece},
publisher = {IEEE},
isbn = {978-1-4577-1484-9},
}