Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman. Clock tree layout design for reduced delay uncertainty. In Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA. pages 179-180, IEEE, 2004. [doi]
@inproceedings{VelenisPF04,
title = {Clock tree layout design for reduced delay uncertainty},
author = {Dimitrios Velenis and Marios C. Papaefthymiou and Eby G. Friedman},
year = {2004},
doi = {10.1109/SOCC.2004.1362399},
url = {http://dx.doi.org/10.1109/SOCC.2004.1362399},
researchr = {https://researchr.org/publication/VelenisPF04},
cites = {0},
citedby = {0},
pages = {179-180},
booktitle = {Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA},
publisher = {IEEE},
isbn = {0-7803-8445-8},
}