Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs

Miroslav N. Velev. Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA. pages 138-147, IEEE Computer Society, 2003. [doi]

Abstract

Abstract is missing.