Miroslav N. Velev. Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction. In 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA. pages 51-56, IEEE Computer Society, 2006. [doi]
@inproceedings{Velev06, title = {Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction}, author = {Miroslav N. Velev}, year = {2006}, doi = {10.1109/ISQED.2006.142}, url = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.142}, tags = {abstraction}, researchr = {https://researchr.org/publication/Velev06}, cites = {0}, citedby = {0}, pages = {51-56}, booktitle = {7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA}, publisher = {IEEE Computer Society}, isbn = {0-7695-2523-7}, }