Andreas G. Veneris, Jiang Brandon Liu. Incremental Design Debugging in a Logic Synthesis Environment. J. Electronic Testing, 21(5):485-494, 2005. [doi]
@article{VenerisL05,
title = {Incremental Design Debugging in a Logic Synthesis Environment},
author = {Andreas G. Veneris and Jiang Brandon Liu},
year = {2005},
doi = {10.1007/s10836-005-0335-9},
url = {http://dx.doi.org/10.1007/s10836-005-0335-9},
tags = {debugging, logic, Meta-Environment, incremental, design},
researchr = {https://researchr.org/publication/VenerisL05},
cites = {0},
citedby = {0},
journal = {J. Electronic Testing},
volume = {21},
number = {5},
pages = {485-494},
}