Ranianand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Uinh Ton, Sergey Shomurryev, Chong Lee, Shoujun Waiig, Huy Ngo, Malik Kdhani, Victor Maruri, Tin Lai, Tam Kpuyeu, Arch Zaliziiyak, Mei Luo, Toan Nguyen, Kazi Asaduzzaman, Siniardeep Maangat, John Lam, Rakesh Patel. Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment. In Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003. pages 659-662, IEEE, 2003. [doi]
@inproceedings{VenkataWTCHLTSL03,
title = {Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment},
author = {Ranianand Venkata and Wilson Wong and Tina Tran and Vinson Chan and Tim Hoang and Henry Lui and Uinh Ton and Sergey Shomurryev and Chong Lee and Shoujun Waiig and Huy Ngo and Malik Kdhani and Victor Maruri and Tin Lai and Tam Kpuyeu and Arch Zaliziiyak and Mei Luo and Toan Nguyen and Kazi Asaduzzaman and Siniardeep Maangat and John Lam and Rakesh Patel},
year = {2003},
doi = {10.1109/CICC.2003.1249481},
url = {https://doi.org/10.1109/CICC.2003.1249481},
researchr = {https://researchr.org/publication/VenkataWTCHLTSL03},
cites = {0},
citedby = {0},
pages = {659-662},
booktitle = {Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003},
publisher = {IEEE},
isbn = {0-7803-7842-3},
}