Ranianand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Uinh Ton, Sergey Shomurryev, Chong Lee, Shoujun Waiig, Huy Ngo, Malik Kdhani, Victor Maruri, Tin Lai, Tam Kpuyeu, Arch Zaliziiyak, Mei Luo, Toan Nguyen, Kazi Asaduzzaman, Siniardeep Maangat, John Lam, Rakesh Patel. Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment. In Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003. pages 659-662, IEEE, 2003. [doi]
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